1. Technical Field
The present invention relates to a design structure. More specifically, it relates a design structure for high performance SRAM (Static Random Access Memory) read bypass for the built-in self-test.
2. Background Information
Built-in self-test (BIST) is a mechanism used within an integrated circuit (IC) to verify all or a portion of the internal functionality of the IC. BIST can reduce the duration of an IC manufacturing test, and, by reducing the number of input/output signals that must be driven or examined under tester control, reduce the complexity of the test setup. Hence, BIST can effectively reduce the cost of IC manufacturing tests. BIST can also be designed to perform field-diagnostics of individual devices or entire systems. For example, it can used to perform a self-diagnostic test for a computer peripheral device (e.g. a printer) at its power-up.
Logic BIST (LBIST) is one type of BIST technology, which is designed for testing random logic. Some LBIST interfaces for SRAM arrays require the ability to test downstream chip logic by bypassing the functional output of the array, and inserting test signals into the SRAM array read output path. FIG. 1 is a diagram illustrating components of a LBIST interface. In FIG. 1, the components for functional output of the SRAM array include an SRAM Dynamic Output unit 101 and a Dynamic to Static Conversion unit 103. A Static Test Logic Unit 102 is used for test purposes. To bypass the functional output, a control unit 104 needs to be implemented. FIG. 1 illustrates a common method of accomplishing the SRAM bypass, in which a multiplexer (the Test Mux 104) is used at the output of the Dynamic to Static Conversion unit 103, and a test signal from the Static Test Logic unit 102 is used to select static test data.
However, when using a multiplexer to bypass the functional output of an SRAM array, extra circuitry is required to be added to the critical output path for SRAM operations, and thus results in an increased delay.